A FinFET transistor is a MOSFET transistor in which a gate electrode is placed on two, three, or four sides of a channel or is wrapped around the channel, with a gate dielectric separating the gate electrode and the channel. A double gate finFET utilizes a double gate configuration in which the gate electrode is placed on two opposite sides of the channel. In a triple gate finFET, the gate electrode is placed on one more side of a typically rectangular channel of the transistor. In a quadruple gate finFET or a wrapped gate finFET, the gate electrode is placed on four sides of the channel. The increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. These devices have been given the generic name “finFETs” because fin sidewalls are used to form a MOSFET. A finFET device has faster switching times, equivalent or higher current density, and much improved short channel control than the mainstream CMOS technology utilizing similar critical dimensions.
In a typical finFET structure, at least one horizontal channel on a vertical sidewall is provided within a semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. Typically, the height of the fin is greater than width of the fin to enable higher on-current per unit area of semiconductor area used for the finFET structure. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is thin enough in a device channel region to ensure forming fully depleted semiconductor devices. Typically, the thickness, or the horizontal width, of a fin in a finFET is less than two-thirds of its gate length in order to obtain good control of the short channel effect.
An inverted U-shaped gate electrode often straddles a central section of the semiconductor fin and covers the gate dielectric layers. In a typical double gate finFET, a gate dielectric layer and a gate conductor are located upon each of the two semiconductor fin sidewalls facing each other. A spacer material of substantial thickness is located between the top surface of the fin and the top portion of the inverted U-shaped gate electrode such that the top surface of the fin is not controlled directly by the portion of the gate electrode above it. In a typical triple gate finFET, a gate electrode of an inverted U shape is typically located upon the two semiconductor fin sidewalls and also upon the top surface of the fin structure. The top surface of the fin is separated from the top portion of the gate electrode only by a gate dielectric layer and is thus controlled by the gate electrode. Ion implantations are performed on the source and drain regions, which are the end portions of the semiconductor fin, to deliver halo, extension, and source/drain doping while using the gate electrode or other masking layer as a mask.
While providing improved MOSFET performance, the finFETs, however, pose unique design challenges. While planar MOSFET devices have virtually no limit on the width of the device above the lithographical minimum dimension and therefore, the size of planar MOSFETs may be adjusted arbitrarily, typical finFETs have identical vertical dimensions for the fins, thereby limiting the size of the finFET to integer multiples of a minimum size finFET for a given channel length. In other words, for the control of the on-current and the off-current of transistors, planar MOSFETs provide two parameters, which are the width, W and the length, L of the channel but finFETs provide only one parameter, which is the length, L of the finFET since the height of the fin, and consequently the width of the channel is fixed for all finFETs. Therefore, for a given transistor length, L, which defines the ratio of the on-current to off-current, the amount of on-current from an individual fin is fixed. Using multiple fins for a finFET provide integer multiples for the total current but non-integer fractions or non-integer multiples of the on-current of an individual fin requires non-obvious or elaborate processing schemes and/or structures. Also, the use of multiple fins tends to use more silicon surface area and makes the device design less area-efficient.
However, transistors with different on-currents are often required in the design of high performance integrated circuits. One such example is a six-transistor SRAM cell, wherein the beta ratio (the ratio of the on-current of a pull-down NFET to the on-current of a pass gate NFET) needs to be kept close to 2 for optimal performance of the SRAM cell.
While it is possible to change the length of finFET devices to reduce the on-current of a finFET as exemplified in Yang et al., “Fully Working 1.25 mm2 6T-SRAM cell with 45 nm gate length Triple Gate Transistors,” IEDM Tech. Dig., 2003, pp. 23-26, the use of longer channel lengths not only consumes more silicon substrate area, but also introduces variables in terms of the variability of the physical dimensions of the gate lengths due to the complexities of optical proximity correction. In addition, different gate lengths give different short channel effect, which can cause threshold voltage mismatching or ratio variation induced by Vdd variation.
Another approach by Aller et al., in U.S. Patent Application Publication No. 2004/0222477 A1 discloses a finFET device provided with a first semiconductor fin and a second semiconductor fin with different heights and adjustments on the ratio of the height of the first semiconductor fin to that of the second semiconductor fin are used to tune the performance of the transistor. However, the use of a thermal oxidation process to reduce the height of the fin requires that a hardmask be used in this process. Many processing steps are necessary such as deposition of a hardmask material, application and lithographic patterning of a photoresist, a transfer of a lithographic pattern into the hardmask, and thermal oxidation. The oxidation raises surface level due to volume expansion caused by the oxidation, which causes vertical variation in the height of the substrate which reduces usable depth of focus during subsequent lithographic process and may cause CD variations in the printed lithographic images.
Therefore, there exists a need for a semiconductor structure and a manufacturing process that produces multiple vertical dimensions for the fins on the same semiconductor wafer. Also, there exists a need for a semiconductor manufacturing process that uses a minimal number of extra processing steps, which are simple and inexpensive.
Also, there exists a need for a dense CMOS circuitry through the use of multiple finFETs with different vertical dimensions for the fins.